Integrated circuit and system with tracking

ABSTRACT

A beamforming IC operates in a transmit mode or a receive mode to respectively transmit and receive signals at different times. To that end, the beamforming IC has an element interface, a transmit branch configured to produce an output transmit signal through the element interface when in the transmit mode, and a receive branch configured to receive an input signal through the element interface when in the receive mode. The beamforming circuit also has a sampling circuit with an electrical coupling with the transmit branch. The sampling circuit is configured to sample the output transmit signal with the electrical coupling to produce a sample signal. The sampling circuit also is configured to direct the sample signal through the receive branch, which is configured to modify the phase of the sample signal to produce a modified sample signal. This modified sample signal can be used to manage the IC transmission.

PRIORITY

This patent application claims priority from provisional U.S. patentapplication No. 62/936,079, filed Nov. 15, 2019, entitled, “BEAMFORMINGINTEGRATED CIRCUIT WITH FEEDBACK TRACKING,” the disclosure of which isincorporated herein, in its entirety, by reference.

FIELD OF THE INVENTION

Illustrative embodiments of the invention relate to integrated circuitsand systems implementing phased arrays and, more particularly,illustrative embodiments of the invention relate to tracking the outputof certain phased arrays.

BACKGROUND

Active electronically steered/scanned antenna systems (“AESA systems,” atype of “phased array system”) or active antenna systems formelectronically steerable beams for a wide variety of radar andcommunications systems. To that end, AESA systems typically have aplurality of beam-forming elements (e.g., antennas) that transmit and/orreceive energy so that such energy can be coherently combined (i.e.,in-phase and amplitude) in a specific direction. This process isreferred to in the art as “beamforming” or “beam steering.”Specifically, for transmission, many AESA systems implement beamsteering by providing various RF phase shift and gain settings. Thephase settings and gain weights together constitute a complex beamweight between each beam-forming element. For a signal receiving mode,many AESA systems use a beamforming or summation point.

To achieve beam-forming using an antenna array, each antenna element isconnected to a semiconductor integrated circuit generally referred to asa “beam-forming IC.” This microchip/integrated circuit may have a numberof sub-circuit components implementing various functions. For example,those components may implement phase shifters, amplitude control modulesor a variable gain amplifier (VGA), a power amplifier, a power combiner,a digital control, and other electronic functions. Such an integratedcircuit is packaged to permit input and output radio frequency (RF)connections.

SUMMARY OF VARIOUS EMBODIMENTS

In accordance with one embodiment of the invention, an IC (e.g., abeamforming IC) operates in one of a transmit mode and a receive mode torespectively transmit and receive signals at different times. To thatend, the IC has an element interface, a transmit branch configured toproduce an output transmit signal through the element interface when inthe transmit mode, and a receive branch configured to receive an inputsignal through the element interface when in the receive mode. Thebeamforming circuit also has a sampling circuit with an electricalcoupling with the transmit branch. The sampling circuit is configured tosample the output transmit signal with the electrical coupling toproduce a sample signal. The sampling circuit also is configured todirect the sample signal through the receive branch, which is configuredto modify the phase of the sample signal to produce a modified samplesignal. This modified sample signal can be used to manage the ICtransmission.

The electrical coupling preferably is formed from a passive circuitelement. To that end, the electrical coupling may be configured topassively sample with the passive circuit element. To produce themodified sample signal, the receive branch may have a receive phaseshifter while the transmit branch has a transmit phase shifter. Thereceive phase shifter and transmit phase shifter may be configured tohave substantially opposite polarities when in the transmit mode. The ICalso may have a summing node configured to electrically combine aplurality of modified sample signals from a plurality of differentreceive branches in the IC.

Among other things, the IC may have a second feedback structure formonitoring transmission from a second element interface of thebeamforming interface. In that case, the IC may have a second transmitbranch configured to produce a second output transmit signal through thesecond element interface when in the transmit mode, and a second receivebranch configured to receive input signals through the second elementinterface when in the receive mode. The IC also may have a secondsampling circuit with second sample output and a second electricalcoupling with the second transmit branch. The second sampling circuit isconfigured to sample the second output transmit signal with the secondelectrical coupling to produce a second sample signal. In addition, thesecond sampling circuit may be configured to direct the second samplesignal through the second receive branch to the second sample output toproduce a second modified sample signal. To control the IC better, theIC also may have a sample controller configured to selectively enablethe IC to either 1) produce the modified sample signal at the sampleoutput or 2) produce the second modified sample signal at the secondsample output. In fact, the sample controller also may be configured toselectively enable the IC to produce both the modified sample signal andthe second modified sample signal at the sample output.

Like other branches, the receive branch may have a receive outputconfigured to forward signals off the IC. To avoid cross-talk or otherinterference, the sampling circuit may have a corresponding sampleoutput that is electrically isolated from the receive output. Thereceive branch also may have a receive amplifier and a receive phaseshifter. To obtain a more accurate sample, the IC may be configured tocause the sample signal to bypass the receive amplifier when in thetransmit mode. Despite that configuration, the receive phase shifter,however, may be configured to receive the sample signal when in thetransmit mode. For similar reasons, the sampling circuit may beconfigured to be electrically isolated from the receive branch when inthe receive mode. In addition, the sampling circuit may be configured tosample the output transmit signal downstream of the transmit amplifier.

In accordance with another embodiment, a beamforming system has a phaseshifter, a plurality of elements, and beamforming IC coupled with theplurality of elements. The beamforming IC has a transmit branchconfigured to produce an output transmit signal when in a transmit mode.The beamforming IC further includes a sampling circuit having anelectrical coupling with the transmit branch. The sampling circuit isconfigured to sample the output transmit signal with the electricalcoupling to produce a sample signal. The sampling circuit also isconfigured to direct the sample signal through the phase shifter toproduce a modified sample signal. In addition, the system further has asubstrate supporting the beamforming IC and a plurality of elementscoupled with the beamforming IC.

In accordance with other embodiments, beamforming method provides abeamforming IC having a transmit branch configured to produce an outputtransmit signal when in a transmit mode and a receive branch configuredto receive an input signal when in a receive mode and having a receiveinterface. The method then electrically couples with the transmit branchwhen in the transmit mode to produce a sample signal, and directs thesample signal through the receive branch to modify the phase of thesample signal, producing a modified sample signal. Next, the methodforwards the modified sample signal from the receive interface.

BRIEF DESCRIPTION OF THE DRAWINGS

Those skilled in the art should more fully appreciate advantages ofvarious embodiments of the invention from the following “Description ofIllustrative Embodiments,” discussed with reference to the drawingssummarized immediately below.

FIG. 1 schematically shows an active electronically steered elementsystem (“AESA system”) configured in accordance with illustrativeembodiments of the invention and communicating with a satellite.

FIGS. 2A and 2B schematically show generalized diagrams of an AESAsystem that may be configured in accordance with illustrativeembodiments of the invention.

FIG. 3A schematically shows a plan view of a laminar printed circuitboard portion of an AESA configured in accordance with illustrativeembodiments of the invention.

FIG. 3B schematically shows a close-up of a portion of the laminatedprinted circuit board of FIG. 3A.

FIG. 4 schematically shows a beamforming system that may implementillustrative embodiments of the invention.

FIGS. 5A-5C schematically show increasing details of a beamformingintegrated circuit that may implement illustrative embodiments of theinvention.

FIG. 6 shows a beamforming process in accordance with illustrativeembodiments of the invention.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Illustrative embodiments enable far field signal monitoring locally;i.e., near or at the beamforming integrated circuit (“BFIC”)transmitting the output signal toward a device in the far field. To thatend, the noted BFIC has a plurality of transmit branches that each areconfigured to produce a local copy of its specified output signal. Eachlocal copy then is phase shifted in a precise manner so that, whencombined with the local copies of other transmit branches of the BFIC,forms a single output signal copy that mimics the actual output signalof the entire BFIC. The system may use this single output signal copyfor a number of beamforming system functions, such as for monitoringpower, calibration, minimizing output signal distortion, etc. Details ofillustrative embodiments are discussed below.

FIG. 1 schematically shows an active electronically steered antennasystem (“AESA system 10”) configured in accordance with illustrativeembodiments of the invention and communicating with an orbitingsatellite 12. A phased array (discussed below and identified byreference number “10A”) implements the primary functionality of the AESAsystem 10. Specifically, as known by those skilled in the art, thephased array forms one or more of a plurality of electronicallysteerable beams that can be used for a wide variety of applications. Asa satellite communication system, for example, the AESA system 10preferably is configured to operate at one or more satellitefrequencies. Among others, those frequencies may include the Ka-band,Ku-band, and/or X-band.

The satellite communication system may be part of a cellular networkoperating under a known cellular protocol, such as the 3G, 4G, or 5Gprotocols. Accordingly, in addition to communicating with satellites,the system may communicate with earth-bound devices, such as smartphonesor other mobile devices, using any of the 3G, 4G, or 5G protocols. Asanother example, the satellite communication system may transmit/receiveinformation between aircraft and air traffic control systems. Of course,those skilled in the art may use the AESA system 10 (implementing thenoted phased array 10A) in a wide variety of other applications, such asbroadcasting, optics, radar, etc. Some embodiments may be configured fornon-satellite communications and instead communicate with other devices,such as smartphones (e.g., using 4G or 5G protocols). Accordingly,discussion of communication with orbiting satellites 12 is not intendedto limit all embodiments of the invention.

FIGS. 2A and 2B schematically show generalized diagrams of the AESAsystem 10 configured in accordance with illustrative embodiments of theinvention. Specifically, FIG. 2A schematically shows a block diagram ofthe AESA system 10, while FIG. 2B schematically shows a cross-sectionalview of a small portion of the same AESA system 10 across line B-B. Thislatter view shows a single silicon integrated circuit 14 mounted onto asubstrate 16 between two transmit, receive, and/or dual transmit/receiveelements 18, i.e., on the same side of a supporting substrate 16 andjuxtaposed with the two elements 18. Note that in some embodiments, suchas some implementing cellular communications, the integrated circuit 14can be coupled with four elements 18. In alternative embodiments,however, the integrated circuit 14 could be on the other side/surface ofthe substrate 16. The AESA system 10 also has a radome 22 toenvironmentally protect the phased array of the system 10. A separateantenna controller 24 (FIG. 2B) electrically connects with the phasedarray to calculate beam steering vectors for the overall phased array,and to provide other control functions.

FIG. 3A schematically shows a plan view of a primary portion of an AESAsystem 10 that may be configured in accordance with illustrativeembodiments of the invention. In a similar manner, FIG. 3B schematicallyshows a close-up of a portion of the phased array 10A of FIG. 3A.

Specifically, the AESA system 10 of FIG. 3A is implemented as a laminarphased array 10A having a laminated printed circuit board 16, such as anFR-4 printed circuit board (i.e., acting as the substrate for routingsignals and also identified by reference number “16”) supporting theabove noted plurality of elements 18 and integrated circuits 14. Theelements 18 preferably are formed as a plurality of square orrectangular patch antennas oriented in a triangular patch arrayconfiguration. In other words, each element 18 forms a triangle with twoother adjacent elements 18. When compared to a rectangular latticeconfiguration, this triangular lattice configuration requires fewerelements 18 (e.g., about 15 percent fewer in some implementations) for agiven grating lobe free scan volume. Other embodiments, however, may useother lattice configurations, such as a pentagonal configuration or ahexagonal configuration. Moreover, despite requiring more elements 18,some embodiments may use a rectangular lattice configuration. Like othersimilar phased arrays, the printed circuit board 16 also may have aground plane (not shown) that electrically and magnetically cooperateswith the elements 18 to facilitate operation.

Indeed, the array shown in FIGS. 3A and 3B is a small phased array 10A.Those skilled in the art can apply principles of illustrativeembodiments to laminar phased arrays 10A with hundreds, or eventhousands of elements 18 and integrated circuits 14. In a similarmanner, those skilled in the art can apply various embodiments tosmaller phased arrays 10A.

As a patch array, the elements 18 have a low profile. Specifically, asknown by those skilled in the art, a patch antenna (i.e., the element 18or the transmission/receiving part of the element) typically is mountedon a flat surface and includes a flat rectangular sheet of metal (knownas the patch and noted above) mounted over a larger sheet of metal knownas a “ground plane.” A dielectric layer between the two metal regionselectrically isolates the two sheets to prevent direct conduction. Whenenergized, the patch and ground plane together produce a radiatingelectric field and/or receive RF signals.

As noted above and discussed in greater detail below, illustrativeembodiments form the patch antennas on one or more printed circuitboards that themselves are coupled with the printed circuit board 16.These patent antennas preferably are formed using standard printedcircuit board fabrication processes, thus complying with standardprinted circuit board design rules (discussed below). Accordingly, usingsuch fabrication processes, each element 18 in the phased array 10Ashould have a very low profile.

The phased array 10A can have one or more of any of a variety ofdifferent functional types of elements 18. For example, the phased array10A can have transmit-only elements 18, receive-only elements 18, and/ordual mode receive and transmit elements 18 (referred to as “dual-modeelements 18”). The transmit-only elements 18 are configured to transmitoutgoing signals (e.g., burst signals) only, while the receive-onlyelements 18 are configured to receive incoming signals only. Incontrast, the dual-mode elements 18 are configured to either transmitoutgoing burst signals, or receive incoming signals, depending on themode of the phased array 10A at the time of the operation. Specifically,when using dual-mode elements 18, the phased array 10A can be in eithera transmit mode, or a receive mode. The noted controller 24 at least inpart controls the mode and operation of the phased array 10A, as well asother array functions.

The AESA system 10 has a plurality of the above noted integratedcircuits 14 (mentioned above with regard to FIG. 2B) for controllingoperation of the elements 18. As noted above, those skilled in the artoften refer to these integrated circuits 14 as “beam steering integratedcircuits,” or “beam forming integrated circuits” (“BFICs 14”).

Each integrated circuit 14 preferably is configured with at least theminimum number of functions to accomplish the desired effect. Indeed,integrated circuits 14 for dual mode elements 18 are expected to havesome different functionality than that of the integrated circuits 14 forthe transmit-only elements 18 or receive-only elements 18. Accordingly,integrated circuits 14 for such non-dual-mode elements 18 typically havea smaller footprint than the integrated circuits 14 that control thedual-mode elements 18. Despite that, some or all types of integratedcircuits 14 fabricated for the phased array 10A can be modified to havea smaller footprint.

As an example, depending on its role in the phased array 10A, eachintegrated circuit 14 may include some or all of the followingfunctions:

-   -   phase shifting,    -   amplitude controlling/beam weighting,    -   switching between transmit mode and receive mode,    -   output amplification to amplify output signals to the elements        18,    -   input amplification for received RF signals (e.g., signals        received from the satellite 12), and    -   power combining/summing and splitting between elements 18.

Indeed, some embodiments of the integrated circuits 14 may haveadditional or different functionality, although illustrative embodimentsare expected to operate satisfactorily with the above noted functions.Those skilled in the art can configure the integrated circuits 14 in anyof a wide variety of manners to perform those functions. For example,the input amplification may be performed by a low noise amplifier, thephase shifting may use conventional active phase shifters, and theswitching functionality may be implemented using conventionaltransistor-based switches.

Each BFIC 14 preferably operates on at least one element 18 in thearray. For example, one BFIC 14 can operate on two or four differentelements 18. Of course, those skilled in the art can adjust the numberof elements 18 sharing an BFIC 14 based upon the application. Forexample, a single BFIC 14 can control two elements 18, three elements18, five elements 18, six elements 18, seven elements 18, eight elements18, etc., or some range of elements 18. Sharing the integrated circuits14 between multiple elements 18 in this manner reduces the requiredtotal number of integrated circuits 14, correspondingly sometimesenabling a reduction in the required size of the printed circuit board16.

As noted above, the dual-mode elements 18 may operate in a transmitmode, or a receive mode. To that end, the integrated circuits 14 maygenerate time division diplex or duplex waveforms so that a singleaperture or phased array 10A can be used for both transmitting andreceiving. In a similar manner, some embodiments may eliminate acommonly included transmit/receive switch in the side arms of the BFIC14. Instead, such embodiments may duplex at the element 18. This processcan be performed by isolating one of the elements 18 between transmitand receive by an orthogonal feed connection.

RF interconnect, through-vias, and/or beam forming lines 23 electricallyconnect the integrated circuits 14 to their respective elements 18. Tofurther minimize the feed loss, illustrative embodiments mount theintegrated circuits 14 as close to their respective elements 18 aspossible. Specifically, this close proximity preferably reduces RFinterconnect line lengths, reducing the feed loss. To that end, eachBFIC 14 preferably is packaged either in a flip-chipped configurationusing wafer level chip scale packaging (WLCSP), or a traditionalpackage, such as quad flat no-leads package (QFN package). While othertypes of packaging may suffice, WLCSP techniques are preferred tominimize real estate on the substrate 16A. Some embodiments may mountsome or all of the integrated circuits 14 on or within the printedcircuit boards 16 supporting the elements 18. Other embodiments maymount some or all of the integrated circuits 14 on the underlyingrouting of the printed circuit board 16.

In addition to reducing feed loss, using WLCSP techniques reduces theoverall footprint of the integrated circuits 14, enabling them to bemounted on the top face of the printed circuit board 16 with theelements 18—providing more surface area for the elements 18.

It should be reiterated that although FIGS. 3A and 3B show the AESAsystem 10 with some specificity (e.g., the layout of the elements 18 andintegrated circuits 14), those skilled in the art may apply illustrativeembodiments to other implementations. For example, as noted above, eachBFIC 14 can connect to more or fewer elements 18, or the latticeconfiguration can be different. Accordingly, discussion of the specificconfiguration of the AESA system 10 of FIG. 3A (and other figures) isfor convenience only and not intended to limit all embodiments.

As noted above, illustrative BFICs 14 more effectively monitor theiroutput transmit signals. In some embodiments, those BFICs 14 monitordual/mode elements 18 although, in some embodiment, the BFICs 14 maymonitor transmit-only elements 18. Accordingly, each BFIC 14 with thisfunctionality has a sampling device that, when in the transmit mode,forms one or more samples of the output transmit signal and feeds thesampled transmit signal back into its temporarily non-used circuitcomponent(s) (e.g., one of its receive branches 46) for processing. Inthis case, the BFIC 14 therefore efficiently makes use of unused receivebranch 46 during the transmit mode to monitor the transmit signalwithout requiring significant additional circuit components. In otherembodiments, rather than using one of the receive branches 46 or any ofits unused circuitry, the BFIC 14 uses additional components (e.g.,additional components) to accomplish the desired function (discussedbelow).

To those ends, FIG. 4 schematically shows the beamforming or AESA system10 configured in accordance with illustrative embodiments of theinvention. Specifically, the system 10 shown has a plurality of BFICs 14that each produce a “sample signal.” In preferred embodiments, the BFICs14 produced their sample signals so they may be relatively easilycombinable on some off-chip combiner 26 on the printed circuit board 16.Preferably, the plurality of sample signals are in phase (e.g., at zeroor 360 degrees) to facilitate their combination. Other embodiments,however, may use combining logic to combine the sample signals when theyare not in-phase.

For a given BFIC 14 or for the system 10 as a whole, the “sample signal”may be an attenuated version or attenuated portion of the outputtransmit signal. Alternatively, the sample signal may be another signalsimilar to, or even the same as, the output transmit signal. In eithercase, the sample signal is formed as a function of the output transmitsignal and thus, can be used to understand characteristics of the outputtransmit signal (e.g., the level of distortion). The term “sample”therefore is not intended to suggest that it digitally samples thesignal, although some embodiments may employ digital sampling whilemonitoring that output signal during BFIC transmission toward the farfield. Accordingly, for each BFIC 14, the sample signal is a signal thatmimics and/or is formed as a function of the actual transmitted signal.Logic can convert this sample signal, if necessary, to an appropriateform for further processing.

FIG. 4 also shows a combiner 26 that forms a system-level sample signal(contrasted against a die-level sample signal produced by each BFIC 14)that may be processed by a downstream processor 28. Among other things,the combiner 26 may be implemented in one or more layers of the printedcircuit board 16 to form an effective, lossy summation node. Forexample, this node may act as an effective Wilkinson power combinercircuit. Accordingly, in a manner similar to each die-level samplesignals, the system-level sample signal preferably is formed to have asingle frequency and phase. As another example, the combiner 26 mayinclude logic that combines the signals in a conventional manner intothe single system-level signal. In some embodiments, the combiner 26 canbe fully on-chip (i.e., on the BFIC 14), fully on the substrate/printedcircuit board 16, or distributed across the BFIC 14

The downstream processor 28 may perform a number of functions, discussedbelow. In this example, the processor 28 includes a down-converter toreduce the frequency of the system-level sample signal for yet furtherprocessing with one or more other processors 28. The processor 28 may beon the printed circuit board 16, or on an off-board system. Moreover,the processor 28 may include a wide variety of other devices. Oneskilled in the art can select the appropriate processor 28 for a desiredapplication. For example, as known by those in the art, a AESA system 10undesirably may distort an intended signal. To ensure the output transitsignal is transmitted as desired, those skilled in the art thus maypre-distort the input transmit signal (e.g., using “digitalpre-distortion”, or “DPD” techniques) in an opposite manner to a knowntransmit distortion, thus canceling out the distortion. Of course, theprocessor 28 uses information from the sample signal to appropriatelypre-distort the output transmit signal.

Accordingly, off-chip circuitry may use the system-level sample signal(or one or more specific die-level sample signals) to reconstruct and/orlearn about the actual characteristics of the relevant transmit signal.Using this information, some embodiments may compare this sample signalwith the desired output transmit signal for applying appropriate DPDtechniques to the input transmit signal (on the system level and/or onthe die level) before it is processed on the integrated circuit 14. Tothat end, the processor 28 may have a DPD block in the system's digitalmodem to pre-distort the input signal as a function of the relevantsample signal. This pre-distortion may be adjusted in real-time (i.e.,during use) and/or set during a calibration step.

Instead of or in addition to the DPD block, the downstream processor 28be implemented as a power monitor to monitor output transmit power inone or more arrays or one or more BFICs 14 (e.g., monitoring EIRP). Inaddition, the downstream processor 28 may monitor the BFICs 14individually for maintaining the general working and health of the AESAsystem 10.

FIGS. 5A-5C schematically show increasing details of one of the BFICs 14implemented in accordance with illustrative embodiments of theinvention. It should be noted that in view of the symmetry of thevarious circuits and to make the figures more readable, FIGS. 5A-5C donot add reference numbers to all transmit branches and their relatedcomponents. Instead, only one branch is labeled, but those skilled inthe art should recognize that similarly positioned and identified blocksin other portions of the drawing has the same reference number.

Specifically, FIG. 5A shows a simple block diagram of a plurality oftransmit branches 30 of a BFIC 14 that produces an output transmitsignal to a remote device, such as the satellite 12 of FIG. 1. To thatend, this figure shows a transmit signal input 32 of the BFIC 14 to aconventional transmit splitter network 34. As known by those in the art,the transmit splitter network 34 splits the input transmit signal into aplurality of signals that each are directed to at least one transmitbranch 30. As discussed below, each transmit branch 30 phase shifts andamplifies its signal for transmission.

In accordance with illustrative embodiments, the BFIC 14 also has asampling circuit 36 configured to produce a modified version of theoutput transmit signal. To that end, the sampling circuit 36 has aplurality of sampling sub-circuits 38 in electrical communication witheach of the transmit branches 30. By way of example, these figuresexplicitly show four sampling sub-circuits 38 that together make up thesampling circuit 36. Each sampling sub-circuit 38 has an electricalcoupler 40 configured to electrically couple to a node or circuitcomponent in the transmit branch 30. Preferably, the electrical coupler40 is near the end of the transmit branch 30, downstream of most activecircuit components, such as the transmit branch phase shifter 42 andamplifier 44 (discussed below). In illustrative embodiments, thatelectrical coupler 40 is configured to capture a version of the transmitsignal to be transmitted from that branch to the far field—that versionis referred to above as the “sample signal.” Those skilled in the artcan select an appropriate electronic coupler to produce the samplesignal.

Preferably, the electrical coupler 40 does not non-negligibly interfereor otherwise distort the actual output transmit signal. To that end, theelectrical coupler 40 may be formed exclusively from passive components(i.e., one or more of capacitance, resistive, and inductive components).Alternatively, the electrical coupler 40 may have both passive and/oractive components, although those in the art should strive to developthe electrical coupler 40 with an acceptably low or minimal interferenceto the output transmit signal in either implementation.

The sampling circuit 36 also has a phase shifter 42 to shift the sampledcircuit, and passes that shifted signal back to a combining network 35that combines the sample signals of all the transmit branches 30 to formthe single (die-level) output sample signal. It is that output samplesignal that those skilled in the art may use to better controltransmission in the far field. FIG. 5B schematically shows more detailsof one embodiment of this general implementation of the four transmitbranches 30 and four corresponding sampling sub-circuits 38. In thatfigure, the circles act as summing nodes 52 (e.g., using Wilkinsoncombiner circuits) to implement the functionality of the combiningnetwork 35 block of FIG. 5A. The output transmit signal is transmittedvia transmit output 53 to the relevant transmit or dual receive/transmitelement 18.

It should be noted that in FIG. 5A, arrows from the transmit signalinput 32 do not pass through the combining network 35 (i.e., thecombining network 35 does not receive those signals) and, instead, passto an input of the transmit splitter network 34. In a similar manner,arrows from the sampling circuit 36 (i.e., the phase shifters 42 of thesampling circuit 36) do not pass through the transmit splitter network34 (i.e., the transmit splitter network 34 does not receive thosesignals) and, instead, pass to an input of the feedback combiningnetwork 35. The arrows are drawn this way to simplify the size andcomplexity of the drawing.

The sampling circuit 36 and other discussed components in FIG. 5A can beon the same die as the BFIC 14, or spread across multiple dies. In asimilar manner, some of the transit branches 30 may not have acorresponding sampling sub-circuit 38 and thus, cannot be managed in amanner similar to the transmit branches 30 having a correspondingsampling sub-circuit 38. Those skilled in the art can select theappropriate implementation as a function of the intended application.

Preferred embodiments do not require extra circuit components toimplement some or all of the sampling circuit 36. Specifically, there isa drive in the art to reduce cost and size of beamforming ICs. Theinventors recognized this and, after experimentation, recognized thatthe receive branches 46 of the BFICs 14 are not used during the transmitmode. To mitigate size, the inventors discovered that they could re-usethe receive branches 46 during their “down time” to assist with transmitoutput signal management. The inventors then realized that with somecareful configuration, they could use the phase shifter 42 and summingnodes (identified by a sigma symbol in the figures) of the receivebranches 46 to produce their sample signals without significantly extracircuitry.

FIG. 5C schematically show more details of this reuse of the receivebranch circuitry. More specifically, to implement its corefunctionality, the BFIC 14 in this figure has four transmit branches 30for transmitting signals, and four parallel receive branches 46 forreceiving signals. This implementation correspondingly has fourtransmit/receive switches (“T/R switches 48”) to alternatively coupleone transmit branch 30 or one receive branch 46 with respective elementinterfaces 53/60. In other words, this integrated circuit 14 may beconsidered to have four transmit and receive branch pairs (“branch pairs50”), and each branch pair 50 forms one of the channels. Each branchpair 50 thus has a single transmit branch 30 and a single receive branch46. The noted T/R switch 48 thus couples the transmit branch 30 to itsrespective element interface 60 when in the transmit mode and,correspondingly, couples the receive branch 46 to that same elementinterface 60 when in the receive mode. Each element interface 60 coupleswith at least one element 18 of the larger AESA system 10.

Instead of using a T/R switch 48, however, some embodiments may useopposite polarity signals for receive and transmission of signals. Forexample, the signals' spatial directions may be ninety degrees out ofphase with each other. Accordingly, such embodiments electrically couplethe element interface 53/60 with both the transmit and receive branches30 and 46, thus omitting the noted T/R switch 48.

Each branch has its conventional components discussed above, and some ofthose components are shown in FIG. 5C. Among other things, thosecomponents include amplifiers 44, phase shifters 42, summing nodes 52,and/or splitting nodes 54. Signals enter and leave the BFIC 14 via aseries of interfaces 53/60. FIG. 5C identifies some of those interfacesschematically in the transmit/receive pair in the lower left corner ofthe circuit. In accordance with illustrative embodiments, each pair oftransmit/receive branches 30/46 includes the above discussed samplingsub-circuit 38 (i.e., at least partly implemented by the respectivereceive branches) to monitor the output signal of its transmit branch 30when in the transmit mode. In this figure, the sampling circuit 36includes the electrical coupler 40, such as a wire (with a terminatingresistor) that inductively or parasitically couples with part of thetransmission line (e.g., adjacent to the beamforming line 23) of thetransmit branch 30. Preferably, as noted above, the electrical coupler40 is physically positioned between the last active electronic device(an amplifier 44 in this case) and the element interface 53/60. In otherwords, the electrical coupler 40 is “downstream” of the amplifier 44 inthis case because it receives a signal from the amplifier 44.

As noted above, rather than using an inductive, non-contact device, thesampling sub-circuits 38 may include a conductive circuit that directlyreceives at least a portion of the output signal. Appropriate signalingand circuitry (e.g., a small voltage divider circuit) may be used toproduce a corresponding result. Accordingly, those in the art may useother types of sampling circuits 36 than those discussed. In this andother embodiments, the sampling circuit 36 is configured so that it doesnot appreciably attenuate or otherwise distort the output transmitsignal.

To use the sampling circuit 36, the integrated circuit 14 also has asample switch 58 (e.g., a single pole, double throw switch) toswitchably connect the sampling sub-circuit 38 with the receive branch46 when in the transmit mode. This switchable connection may beconsidered to be a feedback connection to monitor the output transmitsignal. Moreover, in preferred embodiments, the sampling switch 58couples at or after the output of the amplifier 44 (e.g., a low noiseamplifier) in its respective receive branch 46. By doing this, theintegrated circuit 14 effectively bypasses that low noise amplifier 44,mitigating potential distortion to the sample signal that such amplifier44 undesirably may produce, as well as avoiding significant noise figuredegradation of the receiver due to sampling switch loss in the receivemode.

Accordingly, during the transmit mode, the sampling circuit 36 generatesand transits the sample signal through the (formerly dormant) receivebranch 46 and sums the various sampling signals at various signalsumming nodes 52 in the integrated circuit 14. To ensure that the phaseshifters 42 do not cancel each other out in this multi-channelimplementation, illustrative embodiments change the insertion phase ofthe phase shifters 42 in the receive branch 46 (when in the transmitmode) to be opposite of the respective insertion phases of theirtransmit branches 30. This ensures that the samples from differentbranches combine in phase (e.g., null or max phase), and also ensuresthey obtain a high similarity of the combined sample to the actualradiated signal. As such, when in the transmit mode, the sample signalof each branch pair 50 passes through the various receive branches 46,combine at various summing nodes 52, and are transmitted from theintegrated circuit 14 at a sample output interface 56. This sampleoutput interface 56 may be a dedicated interface to the feedback/samplesignal, or it may share an interface with other functions of the BFIC14.

FIG. 5B schematically shows the phase shifters 42 of each transmitbranch 30 and sampling sub-circuit 38. Traversing counter-clockwisestarting at the top right, the various transmit branches 30 are labeled1A, 2A, 3A, and 4A. Each transmit branch 30 in this example has atransmit branch phase shifter 42 and a sampling sub-circuit phaseshifter 42 (note that the sampling sub-circuit phase shifter 42 can be ashared component with the receive branch 46). Using the branches labeledas “1A,”, the transmit branch phase shifter 42 has a phase phi 1A, whilethe corresponding sampling sub-circuit phase shifter 42 has an oppositephase of negative phi 1A. This makes the phase a null phase. The othertransmit branches 2A, 3A, and 4A have similar phase shiftingrelationships. Accordingly, in this example, the output sample signalwill have a null phase as it is combined from the four in-phase signalsfor the transmit branches 1A-4A. Those skilled in the art, however, mayhave different phase shifting relationships and corresponding logic tostill produce the output sample signal. Various embodiments thereforeare not limited to producing the canceling phase shifts for a nullphase.

When the integrated circuit 14 transitions to the receive mode, the T/Rswitch 48 and the sampling switch 58 both switch to their second,opposite positions. As such, this connects the receive branches 46 tothe element interface 60 and disconnects the sampling circuit 36 fromthe receive branch 46. Accordingly, the sampling circuit 36 iselectrically unconnected to either the transmit or receive branches 30and 46—effectively in an open circuit state. In other words, when in thereceive mode, the sampling circuit 36 is electrically isolated in theintegrated circuit 14. In a corresponding manner, when in the transmitmode, the sampling circuit 36 is electrically coupled with the transmitbranches 30. In preferred embodiments, the sampling circuit output 56 iselectrically isolated from the output of the receive branches 46—thesampling circuit 36 may have its own interface pin on the BFIC 14. Inother embodiments, however, they may share an output interface.

As suggested above, illustrative embodiments may monitor the outputtransmit signal of all of the transmit branches 30 of a single BFIC 14,or the transmit signal for a sub-set of the transmit branches 30 of oneor more BFICs 14. To that end, as shown in FIG. 5B, the BFIC 14 also mayhave a sample controller 62 configured to selectively control switchingin a manner that selectively monitors specific transmit branches 30.Accordingly, for a four branch BFIC 14, the switching controller maymonitor one, two, three, or all four transmit branches 30. Thisselective monitoring can be coordinated across the plurality of BFICs 14of a single AESA system 10 to produce fine-tuned monitoring andmanagement of specific transmit branches of various BFICs 14 across theentire AESA system 10.

It should be reiterated that various embodiments can expand beyond thatshown. For example, the figures show just one polarization forsimplicity. Those skilled in the art may use dual-polarity circuitry andmultiple sample output interfaces 56 for a given transmit branch 30 orBFIC 14, as well as multiple transmit/receive signal interfaces.

FIG. 6 shows a beamforming process in accordance with illustrativeembodiments of the invention. It should be noted that this process issubstantially simplified from a longer process that normally would beused to produce a beamformed signal. Accordingly, the process typicallyhas many that those skilled in the art likely would use. In addition,some of the steps may be performed in a different order than that shown,or at the same time. Those skilled in the art therefore can modify theprocess as appropriate. Moreover, as noted above and below, many of thedevices used to implement the process (e.g., those discussed with regardto FIGS. 5A-5C) are exemplary of a wide variety of different devicesthat may be used. Those skilled in the art can select the appropriatedevices depending upon the application and other constraints.Accordingly, discussion of specific devices is not intended to limit allembodiments.

The process begins at step 600, in which the transmit input 32 (FIGS. 5Band 5C) receives the signal to be transmitted. That signal in turn ispassed through the transmit splitter network 34 of FIG. 5A, which, asshown in FIGS. 5B and 5C, includes a series of splitters that may beimplemented as Wilkinson Splitters or similar devices. After the split,the resultant transmit signals of each branch pass through respectivephase shifters 42 and amplifiers 44, and ultimately pass through thetransmit output or other transmission interface 53 (shown schematicallyin FIG. 5B). The output transmit signal of each branch ultimatelyproduces the final output transmit signal from the array via acorresponding element 18 (e.g., a transmit element 18 or a dualtransmit/receive element 18). At this point, the BFIC 14 is producing aplurality of to-be-combined (using beamforming processes) transmitsignals via each of its branches.

Next, using appropriate switching at step 602, the sampling circuit 36begins sampling the transmit signal to produce a local, “mimicked”version of the transmit signal for each branch. Each branch thenforwards its local sample signal into its corresponding receive branch46 for modification. To that end, the receive branches 46 adjust thephase of their sample signals at step 604 to produce an appropriatelyphased signal that can be combined with other sample signals, andcombines the various branch modified sample signals using the notedcombining network 35 (step 606).

At this point in the process, the BFIC 14 has a single sample signal toforward off-chip toward the system-level combining node/device, which,as noted above, preferably is a node in the substrate/printed circuitboard 16 (step 608). The process concludes at step 610, in which theprocess manages the system 10 with the combined sample signal. Amongother things and as noted above, this combined sample signal enables thesystem 10 to detect output transmit signal distortions, thus permittingthe system 10 to pre-distort the input transmit signal to compensate forsuch discovered distortion. As such, the ultimate signal transmitted maybe closer to the idealized output transmit signal. This processpreferably is performed in real-time, during use.

Accordingly, illustrative embodiments enable local far-field transmitsignal monitoring. Such processes may efficiently reuse temporarilydormant circuitry already on the BFIC 14 to effectively monitorfar-field transmit signals.

The embodiments of the invention described above are intended to bemerely exemplary; numerous variations and modifications will be apparentto those skilled in the art, such as applications to other types ofintegrated circuits beyond BFICs 14. Such variations and modificationsare intended to be within the scope of the present invention as definedby any of the appended claims. Some embodiments contemplate applyingvarious combinations of the claims together.

What is claimed is:
 1. An IC having a transmit mode and a receive mode,the IC comprising: an element interface; a transmit branch configured toproduce an output transmit signal through the element interface when inthe transmit mode; a receive branch configured to receive an inputsignal through the element interface when in the receive mode; and asampling circuit having an electrical coupling with the transmit branch,the sampling circuit configured to sample the output transmit signalwith the electrical coupling to produce a sample signal, the samplingcircuit configured to direct the sample signal through the receivebranch, the receive branch configured to modify the phase of the samplesignal to produce a modified sample signal.
 2. The IC as defined byclaim 1 wherein the electrical coupling comprises a passive circuitelement.
 3. The IC as defined by claim 2 wherein the electrical couplingis configured to passively sample with the passive circuit element. 4.The IC as defined by claim 1 wherein the receive branch has a receivephase shifter and the transmit branch has a transmit phase shifter, thereceive phase shifter and transmit phase shifter configured to haveopposite polarities when in the transmit mode.
 5. The IC as defined byclaim 1 further comprising: a second element interface; a secondtransmit branch configured to produce a second output transmit signalthrough the second element interface when in the transmit mode; a secondreceive branch configured to receive input signals through the secondelement interface when in the receive mode; a second sampling circuithaving second sample output and a second electrical coupling with thesecond transmit branch, the second sampling circuit configured to samplethe second output transmit signal with the second electrical coupling toproduce a second sample signal; and the second sampling circuitconfigured to direct the second sample signal through the second receivebranch to the second sample output to produce a second modified samplesignal; and a sample controller configured to selectively enable the ICto either 1) produce the modified sample signal at the sample output or2) produce the second modified sample signal at the second sampleoutput, the sample controller further configured to selectively enablethe IC to produce both the modified sample signal and the secondmodified sample signal at the sample output.
 6. The IC as defined byclaim 1 further comprising a summing node configured to electricallycombine a plurality of modified sample signals from a plurality ofdifferent receive branches in the IC, the summing node being part of thereceive branch.
 7. The IC as defined by claim 1 wherein the receivebranch comprises a receive output configured to forward signals off theIC, the sampling circuit having a sample output that is electricallyisolated from the receive output.
 8. The IC as defined by claim 1wherein the receive branch comprises a receive amplifier and a receivephase shifter, the IC being configured to cause the sample signal tobypass the receive amplifier when in the transmit mode, the receivephase shifter receiving the sample signal when in the transmit mode. 9.The IC as defined by claim 1 wherein the receive branch comprises areceive amplifier, the IC being configured to bypass the amplifier whenin the transmit mode.
 10. The IC as defined by claim 1 wherein thesampling circuit is configured to be electrically isolated from thereceive branch when in the receive mode.
 11. The IC as defined by claim1 wherein the transmit branch has a transmit amplifier, the samplingcircuit being configured to sample the output transmit signal downstreamof the transmit amplifier.
 12. A beamforming system comprising: aplurality of elements; a phase shifter; a beamforming IC coupled withthe plurality of elements, the beamforming IC having a transmit branchconfigured to produce an output transmit signal when in a transmit mode,the beamforming IC further comprising a sampling circuit having anelectrical coupling with the transmit branch, the sampling circuitconfigured to sample the output transmit signal with the electricalcoupling to produce a sample signal, the sampling circuit configured todirect the sample signal through the phase shifter to produce a modifiedsample signal; and a substrate supporting the beamforming IC and theplurality of elements.
 13. The beamforming system as defined by claim 12further comprising a plurality of beamforming ICs producing a pluralityof output sampling signals, the substrate comprising a system summingnode configured to receive and sum the plurality of output samplingsignals.
 14. The beamforming system as defined by claim 13 wherein thesubstrate comprises a printed circuit board having a plurality ofconductive layers, the plurality of conductive layers comprising thesystem summing node.
 15. The beamforming system as defined by claim 12further comprising a digital pre-distorter operably coupled with thebeamforming IC to receive the modified sample signal, the digitalpre-distorter also being operatively coupled with the beamforming IC topre-distort the output transmit signal as a function of the receivedmodified sample signal.
 16. The beamforming system as defined by claim12 further comprising a circuit monitor configured to monitor transmitoutput power of the transmit branch.
 17. The beamforming system asdefined by claim 12 wherein the IC has a sample output, further whereinthe sampling circuit is configured to direct the sample signal throughthe receive branch to produce the modified sample signal and direct themodified sample signal toward the sample output.
 18. The beamformingsystem as defined by claim 12 wherein the electrical coupling isconfigured to passively sample with a passive circuit element.
 19. Thebeamforming system as defined by claim 12 wherein the beamforming IC hasa plurality of transmit branches and a plurality of output interfaceseach coupled with one transmit branch, the beamforming IC beingconfigured to selectively enable the sampling circuit to couple with oneor more of the plurality of transmit branches.
 20. The beamformingsystem as defined by claim 12 wherein the receive branch has a receivephase shifter and the transmit branch has a transmit phase shifter, thereceive phase shifter and transmit phase shifter configured to havesubstantially opposite polarities when in the transmit mode.
 21. Thebeamforming system as defined by claim 12 wherein the beamforming IC hasa receive branch with a receive phase shifter and configured to receivean input signal when in a receive mode, the phase shifter comprising thereceive phase shifter.
 22. A beamforming method comprising: providing abeamforming IC having a transmit branch configured to produce an outputtransmit signal when in a transmit mode and a receive branch configuredto receive an input signal when in a receive mode and having a receiveinterface; electrically coupling with the transmit branch when in thetransmit mode to produce a sample signal; directing the sample signalthrough the receive branch to modify the phase of the sample signal toproduce a modified sample signal; and forwarding the modified samplesignal from the receive interface.
 23. The beamforming method as definedby claim 22 wherein forwarding the modified sample signal comprisesdirecting the modified sample signal to a processor.
 24. The beamformingmethod as defined by claim 23 wherein the processor comprises a digitalpre-distorter or a power monitor.
 25. The beamforming method as definedby claim 22 further comprising distorting the output transmit signal,via the transmit branch, as a function of the modified sample signal.26. The beamforming method as defined by claim 22 further comprisingreceiving a plurality of modified sample signals from the beamforming ICand summing the plurality of modified sample signals, summing beingperformed on the beamforming IC.
 27. The beamforming method as definedby claim 22 wherein the beamforming IC is mounted on a substrate havinga plurality of elements and other beamforming ICs, the method furthercomprising receiving a plurality of modified sample signals from thebeamforming IC and other beamforming ICs and summing the plurality ofmodified sample signals, summing being performed on the substrate. 28.The beamforming method as defined by claim 22 further wherein thetransmit branch has a transmit phase shifter having a transmit phase,the receive phase shifter having a receive phase shifter with a receivephase, the receive phase and transmit phase being substantially oppositephases when in the transmit mode to produce the modified sample signal.